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ADE7751
Parameter
Value
Unit
Test Conditions/Comments
LOGIC OUTPUTS
4
F1 and F2
Output High Voltage, V OH
I SOURCE = 10 mA
Output Low Voltage, V OL
CF, FAULT, and REVP
Output High Voltage, V OH
Output Low Voltage, V OL
POWER SUPPLY
4.5
0.5
4
0.5
V min
V max
V min
V max
DV DD = 5 V
I SINK = 10 mA
DV DD = 5 V
I SOURCE = 5 mA
DV DD = 5 V
I SINK = 5 mA
DV DD = 5 V
For Specified Performance
AV DD
DV DD
AI DD
DI DD
4.75
5.25
4.75
5.25
3
2.5
V min
V max
V min
V max
mA max
mA max
5 V – 5%
5 V + 5%
5 V – 5%
5 V + 5%
Typically 2 mA
Typically 1.5 mA
NOTES
1
2
3
4
See Terminology section for explanation of specifications.
See plots in Typical Performance Characteristics graphs.
See Fault Detection section of data sheet for explanation of fault detection functionality.
Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
TIMING CHARACTERISTICS 1, 2
(AV DD = DV DD = 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.58 MHz,
T MIN to T MAX = –40 C to +85 C.)
Parameter
Value
Unit
Test Conditions/Comments
t 1
3
275
ms
F1 and F2 Pulsewidth (Logic Low)
t 2
t 3
t 4 3
t 5
t 6
See Table III
1/2 t 2
90
See Table IV
CLKIN/4
sec
sec
ms
sec
sec
Output Pulse Period. See Transfer Function section.
Time Between F1 Falling Edge and F2 Falling Edge
CF Pulsewidth (Logic High)
CF Pulse Period. See Transfer Function section.
Minimum Time Between F1 and F2 Pulse
NOTES
1
2
3
Sample tested during initial release and after any redesign or process change that may affect this parameter.
See Figure 1.
The pulsewidths of F1, F2, and CF are not fixed for higher output frequencies. See Frequency Outputs F1 and F2 section.
Specifications subject to change without notice.
t 1
F1
. t 6
. t 2
F2
t 4
. t 3
. t 5
CF
Figure 1. Timing Diagram for Frequency Outputs
REV. 0
–3 –
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